\doxysection{I2\+C\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_i2_c___type_def}{}\label{struct_i2_c___type_def}\index{I2C\_TypeDef@{I2C\_TypeDef}}


Inter-\/integrated Circuit Interface.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a91782f7b81475b0e3c3779273abd26aa}{CR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a29eb47db03d5ad7e9b399f8895f1768c}{CR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_ae8269169fcbdc2ecb580208d99c2f89f}{OAR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a73988a218be320999c74a641b3d6e3c1}{OAR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a92514ade6721d7c8e35d95c5b5810852}{TIMINGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a95f1607b6254092066a3b6e35146e28a}{TIMEOUTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a0f73f2b049d95841c54313f0cc949afe}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a790a1957ec69244915a9637f7d925cf7}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a64c9036c1b58778cda97efa2e8a4be97}{PECR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_a43d30d8efd8e4606663c7cb8d2565e12}{RXDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_i2_c___type_def_ad243ba45c86b31cb271ccfc09c920628}{TXDR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Inter-\/integrated Circuit Interface. 

\label{doc-variable-members}
\Hypertarget{struct_i2_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_i2_c___type_def_a91782f7b81475b0e3c3779273abd26aa}\index{I2C\_TypeDef@{I2C\_TypeDef}!CR1@{CR1}}
\index{CR1@{CR1}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR1}{CR1}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a91782f7b81475b0e3c3779273abd26aa} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+CR1}

I2C Control register 1, Address offset\+: 0x00 \Hypertarget{struct_i2_c___type_def_a29eb47db03d5ad7e9b399f8895f1768c}\index{I2C\_TypeDef@{I2C\_TypeDef}!CR2@{CR2}}
\index{CR2@{CR2}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR2}{CR2}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a29eb47db03d5ad7e9b399f8895f1768c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+CR2}

I2C Control register 2, Address offset\+: 0x04 \Hypertarget{struct_i2_c___type_def_a790a1957ec69244915a9637f7d925cf7}\index{I2C\_TypeDef@{I2C\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a790a1957ec69244915a9637f7d925cf7} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+ICR}

I2C Interrupt clear register, Address offset\+: 0x1C \Hypertarget{struct_i2_c___type_def_a0f73f2b049d95841c54313f0cc949afe}\index{I2C\_TypeDef@{I2C\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a0f73f2b049d95841c54313f0cc949afe} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+ISR}

I2C Interrupt and status register, Address offset\+: 0x18 \Hypertarget{struct_i2_c___type_def_ae8269169fcbdc2ecb580208d99c2f89f}\index{I2C\_TypeDef@{I2C\_TypeDef}!OAR1@{OAR1}}
\index{OAR1@{OAR1}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OAR1}{OAR1}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_ae8269169fcbdc2ecb580208d99c2f89f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+OAR1}

I2C Own address 1 register, Address offset\+: 0x08 \Hypertarget{struct_i2_c___type_def_a73988a218be320999c74a641b3d6e3c1}\index{I2C\_TypeDef@{I2C\_TypeDef}!OAR2@{OAR2}}
\index{OAR2@{OAR2}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OAR2}{OAR2}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a73988a218be320999c74a641b3d6e3c1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+OAR2}

I2C Own address 2 register, Address offset\+: 0x0C \Hypertarget{struct_i2_c___type_def_a64c9036c1b58778cda97efa2e8a4be97}\index{I2C\_TypeDef@{I2C\_TypeDef}!PECR@{PECR}}
\index{PECR@{PECR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PECR}{PECR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a64c9036c1b58778cda97efa2e8a4be97} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+PECR}

I2C PEC register, Address offset\+: 0x20 \Hypertarget{struct_i2_c___type_def_a43d30d8efd8e4606663c7cb8d2565e12}\index{I2C\_TypeDef@{I2C\_TypeDef}!RXDR@{RXDR}}
\index{RXDR@{RXDR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RXDR}{RXDR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a43d30d8efd8e4606663c7cb8d2565e12} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+RXDR}

I2C Receive data register, Address offset\+: 0x24 \Hypertarget{struct_i2_c___type_def_a95f1607b6254092066a3b6e35146e28a}\index{I2C\_TypeDef@{I2C\_TypeDef}!TIMEOUTR@{TIMEOUTR}}
\index{TIMEOUTR@{TIMEOUTR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TIMEOUTR}{TIMEOUTR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a95f1607b6254092066a3b6e35146e28a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+TIMEOUTR}

I2C Timeout register, Address offset\+: 0x14 \Hypertarget{struct_i2_c___type_def_a92514ade6721d7c8e35d95c5b5810852}\index{I2C\_TypeDef@{I2C\_TypeDef}!TIMINGR@{TIMINGR}}
\index{TIMINGR@{TIMINGR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TIMINGR}{TIMINGR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_a92514ade6721d7c8e35d95c5b5810852} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+TIMINGR}

I2C Timing register, Address offset\+: 0x10 \Hypertarget{struct_i2_c___type_def_ad243ba45c86b31cb271ccfc09c920628}\index{I2C\_TypeDef@{I2C\_TypeDef}!TXDR@{TXDR}}
\index{TXDR@{TXDR}!I2C\_TypeDef@{I2C\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TXDR}{TXDR}}
{\footnotesize\ttfamily \label{struct_i2_c___type_def_ad243ba45c86b31cb271ccfc09c920628} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t I2\+C\+\_\+\+Type\+Def\+::\+TXDR}

I2C Transmit data register, Address offset\+: 0x28 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
